The DRAM (Dynamic Random Access Memory) has been mainly used as a general-purpose and high-capacity semiconductor memory device. Memory cells in the DRAM are placed at the intersections between a plurality of word lines and a plurality of bit lines arranged in matrix on a main surface of a semiconductor substrate, and each is composed of one memory cell selecting MISFET and one capacitive element (capacitor) connected to this MISFET in series. The memory cell selecting MISFET is mainly composed of a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions constituting a source and a drain. The bit line is arranged on the memory cell selecting MISFET and electrically connected to one of the source and drain. Similarly, a data storage capacitor is arranged on the memory cell selecting MISFET and electrically connected to the other of the source and drain.
Japanese Patent Laid-Open No. 5-110019 discloses a one-transistor and one-capacitor semiconductor memory device in which a trench capacitor is formed in a semiconductor substrate and a vertical MIS transistor is arranged thereon.
Japanese Patent Laid-Open No. 11-87541 discloses another vertical MISFET, which is different from that shown in Japanese Patent Laid-Open No. 5-110019. In this vertical MISFET, a columnar laminated structure made of poly-crystalline silicon is provided on a semiconductor substrate, and a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) are formed in this order from below in the laminated structure. A sidewall of the intermediate semiconductor layer functions as a channel region and a gate insulating film is formed on the surface of the sidewall. Also, a gate electrode is formed on the sidewall of the laminated structure via the above-mentioned gate insulating film.